ST STM32F101 series Reference Manual page 133

Connectivity line devices: reset and clock control (RCC)
Bit 27 PLL2RDY: PLL2 clock ready flag
Bit 26 PLL2ON: PLL2 enable
Bit 25 PLLRDY: PLL clock ready flag
Bit 24 PLLON: PLL enable
Bits 23:20
Bit 19 CSSON: Clock security system enable
Bit 18 HSEBYP: External high-speed clock bypass
Bit 17 HSERDY: External high-speed clock ready flag
Bit 16 HSEON: HSE clock enable
Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
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Set by hardware to indicate that the PLL2 is locked.
0: PLL2 unlocked
1: PLL2 locked
Set and cleared by software to enable PLL2.
Cleared by hardware when entering Stop or Standby mode. This bit can not be cleared if the
PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used
as system clock).
0: PLL2 OFF
1: PLL2 ON
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock. Software
must disable the USB OTG FS clock before clearing this bit.
0: PLL OFF
1: PLL ON
Reserved, must be kept at reset value.
Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if a HSE clock failure is detected.
0: Clock detector OFF
1: Clock detector ON (Clock detector ON if the HSE oscillator is ready, OFF if not)
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit
can be written only if the HSE oscillator is disabled.
0: external 3-25 MHz oscillator not bypassed
1: external 3-25 MHz oscillator bypassed with external clock
Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the
HSE oscillator clock to fall down after HSEON reset.
0: HSE oscillator not ready
1: HSE oscillator ready
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
These bits are initialized automatically at startup.
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