ST Sitronix ST7038 Manual
ST Sitronix ST7038 Manual

ST Sitronix ST7038 Manual

Dot matrix lcd controller/driver

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Sitronix
FEATURES
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5 x 8 dot matrix possible
Support low voltage single power operation:
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Ø
VDD, VDD2: 1.8 to 3.3V (typical)
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LCD Voltage Operation Range (V0/Vout)
Ø
Programmable V0: 3 to 7V(V0)
Ø
External power applied: Max. 12V(Vout)
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Interface
Ø
6800-4bit / 8bit interface
8080-4bit / 8bit interface
Ø
Ø
3-line serial interface
Ø
4-line serial interface
2
Ø
I
C interface
Support display mode:
l
Ø
8-COM x 100-SEG and 80 ICON
16-COM x 100-SEG and 80 ICON
Ø
Ø
24-COM x 80-SEG and 80 ICON
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10,240-bit Character Generator ROM
(CGROM) stores 256 character fonts
GENERAL DESCRIPTION
ST7038 dot-matrix liquid crystal display controller can
display alphanumeric, Japanese kana characters and
symbols. It can be configured to drive a dot-matrix liquid
crystal display under the control of a microprocessor with
4/8-bit 6800-series or 8080-series, 3/4-line serial or fast I
interface. Since all the functions (such as display RAM,
character generator ROM/RAM and liquid crystal driver)
required for driving a dot-matrix liquid crystal display are
internally embedded in this chip, a minimal system can be
used with this controller/driver.
The Character Generator ROM of ST7038 has 256 5x8dot
cells and stores 256 different character fonts (5x8dot).
Product Name
ST7038-0B
ST7038
ST7038i
Ver 1.1
Character generator ROM Size
256
6800-4bit / 8bit interface
8080-4bit / 8bit interface
3-line/4-line serial interface
2
(without I
C interface)
2
I
C interface
Dot Matrix LCD Controller/Driver
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64 x 8-bit Character Generator RAM
(CGRAM)
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80 x 8-bit Display RAM (80 characters max.)
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16 x 5 bit ICON RAM
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Variable instruction functions:
clear display, return home, display ON/OFF,
cursor ON/OFF, character blink, cursor shift,
display shift, double height font, ICON control
and character generation RAM
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Reset circuit through an external reset pin
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Internal oscillator or external clock
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Built-in low power consumption voltage
booster, regulator and follower circuit
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Built-in high-accuracy voltage regulator:
Programmable output range: 3~7V
Ø
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COM/SEG direction selectable by instruction
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Selectable CGRAM/CGROM size
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Package Type: COG
ST7038 is suitable for low voltage supply (1.8V to 3.3V) and
is perfectly suitable for any portable product which is driven
by the battery and requires low power consumption.
2
C
The display resolution of ST7038 dot-matrix LCD driver can
be either 1-line x 20 characters, 2-line x 20 characters or
3-line x 16 characters with 80-bit ICON.
ST7038 works alone without extra cascaded drivers.
1/61
ST
ST7038
Support Character
English / Europe / Japan
2007/01/25

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Summary of Contents for ST Sitronix ST7038

  • Page 1 Sitronix ST7038 Dot Matrix LCD Controller/Driver FEATURES 5 x 8 dot matrix possible 64 x 8-bit Character Generator RAM Support low voltage single power operation: (CGRAM) Ø 80 x 8-bit Display RAM (80 characters max.) VDD, VDD2: 1.8 to 3.3V (typical) LCD Voltage Operation Range (V0/Vout) 16 x 5 bit ICON RAM Ø...
  • Page 2 ST7038 PAD ARRANGEMENT Chip Size: 5476.2um X 906.2 um Bump Pitch: I/O PAD: 73um COM/SEG PAD: 45um Bump size: PAD No. 001 ~ 057: 55um X 60um PAD No. 058 ~ 175: 30um X 80um Bump Height: 17um Chip Thickness: 480um Ver 1.1 2/61...
  • Page 3 ST7038 PAD CENTER COORDINATES (3-line & 2-line with double height) Unit: um PAD No. PIN Name PAD No. PIN Name XRESET 2543.915 -2126.56 2424.915 -2199.56 2350.675 -2272.56 A0(RS) 2276.575 COM[12] -2611.93 -369 2157.575 COM[11] -2566.93 -369 /WR(RW) 2084.575 COM[10] -2521.93 -369 /RD(E) 1965.575...
  • Page 4 ST7038 PAD No. PIN Name PAD No. PIN Name SEG[33] -316.93 -369 COM[14] 2158.07 -369 SEG[34] -271.93 -369 COM[15] 2203.07 -369 SEG[35] -226.93 -369 COM[16] 2248.07 -369 SEG[36] -181.93 -369 COM[17] 2293.07 -369 SEG[37] -136.93 -369 COM[18] 2338.07 -369 SEG[38] -91.93 -369 COM[19]...
  • Page 5 ST7038 PAD CENTER COORDINATES (2-line & 1-line with double height) Unit: um PAD No. PIN Name PAD No. PIN Name XRESET 2543.915 -2126.56 2424.915 -2199.56 2350.675 -2272.56 A0(RS) 2276.575 COM[8] -2611.93 -369 2157.575 COM[7] -2566.93 -369 /WR(RW) 2084.575 COM[6] -2521.93 -369 /RD(E) 1965.575...
  • Page 6 ST7038 PAD No. PIN Name PAD No. PIN Name SEG[43] -316.93 -369 SEG[98] 2158.07 -369 SEG[44] -271.93 -369 SEG[99] 2203.07 -369 SEG[45] -226.93 -369 SEG[100] 2248.07 -369 SEG[46] -181.93 -369 COM[9] 2293.07 -369 SEG[47] -136.93 -369 COM[10] 2338.07 -369 SEG[48] -91.93 -369 COM[11]...
  • Page 7 ST7038 PAD CENTER COORDINATES (1-line, SHLC=“H”) Unit: um PAD No. PIN Name PAD No. PIN Name XRESET 2543.915 -2126.56 2424.915 -2199.56 2350.675 -2272.56 A0(RS) 2276.575 COM[8] -2611.93 -369 2157.575 COM[7] -2566.93 -369 /WR(RW) 2084.575 COM[6] -2521.93 -369 /RD(E) 1965.575 COM[5] -2476.93 -369 DB[0]...
  • Page 8 ST7038 PAD No. PIN Name PAD No. PIN Name SEG[43] -316.93 -369 SEG[98] 2158.07 -369 SEG[44] -271.93 -369 SEG[99] 2203.07 -369 SEG[45] -226.93 -369 SEG[100] 2248.07 -369 SEG[46] -181.93 -369 2293.07 -369 SEG[47] -136.93 -369 2338.07 -369 SEG[48] -91.93 -369 2383.07 -369 SEG[49]...
  • Page 9 ST7038 PAD CENTER COORDINATES (1-line, SHLC=“L”) Unit: um PAD No. PIN Name PAD No. PIN Name XRESET 2543.915 -2126.56 2424.915 -2199.56 2350.675 -2272.56 A0(RS) 2276.575 -2611.93 -369 2157.575 -2566.93 -369 /WR(RW) 2084.575 -2521.93 -369 /RD(E) 1965.575 -2476.93 -369 DB[0] 1892.575 -2431.93 -369 DB[1]...
  • Page 10 ST7038 PAD No. PIN Name PAD No. PIN Name SEG[43] -316.93 -369 SEG[98] 2158.07 -369 SEG[44] -271.93 -369 SEG[99] 2203.07 -369 SEG[45] -226.93 -369 SEG[100] 2248.07 -369 SEG[46] -181.93 -369 COM[8] 2293.07 -369 SEG[47] -136.93 -369 COM[7] 2338.07 -369 SEG[48] -91.93 -369 COM[6]...
  • Page 11: Block Diagram

    ST7038 BLOCK DIAGRAM XRESET Reset Timing circuit generator Instruction register(IR) Instruction COM1 to Display data decoder COM16 24-bit Common (or 24) (DDRAM) shift signal register driver 80x8 bits COMI interface Address SEG1 to counter SEG100 (AC) 100-bit 100-bit Segment (or 80) shift latch signal...
  • Page 12: Pin Description

    ST7038 PIN DESCRIPTION Interfaced Name Function with External reset pin. XRESET Low active. Register select. 0: Instruction register (for writing) A0(RS) Busy flag & address counter (for reading) 1: Data register (for write and read) This Pin must connect to “VDD” when it is not used 8080-series interface (/WR): Write enable signal input pin (low active).
  • Page 13 ST7038 Interfaced Name Function with Common driver outputs. COM1~COM16 Signals that are not used will output the non-selection waveform. For (COM1~COM24) example, COM9 to COM16 output the non-selection waveform in 1-line display mode. COMI1, COMI2 Common driver outputs for ICON. Segment driver outputs.
  • Page 14: Function Description

    ST7038 FUNCTION DESCRIPTION MICROPROCESSOR INTERFACE Chip Select Input The CSB pin is used for chip selection. ST7038 can interface with an MPU when CSB is "L". When CSB is set to “H”, the control signal inputs, A0, /RD(E) and /WR(R/W), are disabled and DB0 to DB7 are set to be high impedance. When using 3-line or 4-line serial interface, the internal shift register and counter are reset right after the falling edge of CSB.
  • Page 15: Bit Transfer

    ST7038 Figure 1 The 4-Line SPI Mode access timing Figure 2 The 3-Line SPI Mode access timing C Interface (PS[2:0] = "1, 0, 0") The I C Interface uses two-signal to communicate between different ICs or modules. The two signals are SDA (Serial Data) and SCL (Serial Clock).
  • Page 16 ST7038 ACKNOWLEDGEMENT Acknowledge signal (ACK) is not identical with the Busy Flag (BF) signal in parallel interface. Since internal status cannot be read out, a certain delay is needed before writing the next instructions/data. Each byte of 8-bit is followed by an acknowledge bit. To check the acknowledge bit, the transmitter must release SDA to HIGH first and then the master generates an extra acknowledge related clock pulse for the acknowledge bit.
  • Page 17: Operation

    ST7038 C Interface protocol ST7038 receives command/data issued by MPU with correct slave address. Before any data is transmitted on the I Interface, the device, which should respond, is addressed first. Four kinds of 7-bit slave address (0111100 to 0111111) are reserved for ST7038.
  • Page 18 ST7038 Busy Flag (BF) When BF is "High” (Busy), it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read in parallel interface mode. By issuing A0=”Low” and R/W=”High” (Read Status operation), BF (Busy Flag) can be checked on DB7.
  • Page 19 ST7038 2-LINE DISPLAY (N2=0, N1=1) In this mode, each line can use 40 RAM-cells to store the display data. The relation between DDRAM address and display position is illustrated in Figure 11 (NOTE: The end address of the first line and the start address of the second line are not consecutive).
  • Page 20 ST7038 3-LINE DISPLAY (N2=1, N1=0) In this mode, each line can use 16 RAM-cells to store the display data. The relation between DDRAM address and display position is illustrated in Figure 13. For example, 16 characters by 3 lines are displayed (with 80 segments); the default relation between DDRAM Address and display position is illustrated on the top of Figure 14.
  • Page 21: Character Generator Rom (Cgrom)

    ST7038 Character Generator ROM (CGROM) The Character Generator ROM stores 5x8-dot character patterns for 8-bit character codes. It stores 256 5x8-dot character patterns which can be selected by 8-bit character code (Table 5). The first 16 patterns are multiplexed with the Character Generator RAM (CGRAM).
  • Page 22 ST7038 Character Generator RAM (CGRAM) The Character Generator RAM is reserved for customers to rewrite character patterns by program. Total 8 character patterns (each one is 5x8-dot) can be stored in CGRAM. Each byte of CGRAM has 5 bits and a character pattern (5x8-bit) uses 8 bytes to store its pattern.
  • Page 23 ST7038 Table 7 Use OPR2 & OPR1 to configure the mapping between CGRAM and CGROM Ver 1.1 23/61 2007/01/25...
  • Page 24 ST7038 ICON RAM There are 80 bits ICON RAM embedded in ST7038. Each bit is mapped to an ICON pixel. Write “1”/”0” into the ICON RAM to control the ICON ON/OFF. Refer to Table 8 for the relationship between ICON RAM address and ICON mapping. ICON RAM Mapping when SHLS=1: ICON RAM bits ICON Address...
  • Page 25 ST7038 LCD Driver Circuit ST7038 LCD Driver Circuit has 3 kinds of output mode: 8+1 common outputs, 16+1 common outputs and 24+1 common outputs. Besides, ST7038 also support horizontal and vertical mirror feature. Please refer to for the relationship of Pin Number and Pin Function.
  • Page 26: Instruction Code

    ST7038 INSTRUCTIONS Instruction Code Execution Time OSC= OSC= OSC= Instruction Description 260.4K 284.1K 531.1K Default Instruction Table (IS[1:0]: Don’t Care) Write "20H" to clear DDRAM and set Clear Display AC to "00H". Set AC to "00H". It will return cursor to the original position if shifted.
  • Page 27 ST7038 Instruction table 1: IS[1:0]=(0,1) BS2~1: Bias select; Follower Control OPF2~1: Select built-in voltage 93 us 85 us 70us follower circuit. Set ICON RAM Set ICON address into AC (address 93 us 85 us 70 us Address counter). PD: Power down; V0 Control 1 93us 85us...
  • Page 28: Instruction Description

    ST7038 INSTRUCTION DESCRIPTION IS[1:0]: Don’t Care Clear Display Clear all the display data by writing "20H" (space code) to all DDRAM address. Then set DDRAM address "00H" into AC (address counter). This (AC=00H) will return cursor to the original position, namely, bring the cursor to the left edge on first line of the display.
  • Page 29: Display Control

    ST7038 Display Control Set Display and Cursor mode. D: Display ON/OFF control bit. D = "1", the display is turned on. D = "0", the display is turned off, but display data is remained in DDRAM. C: Cursor ON/OFF control bit. C = "1", cursor is turned on.
  • Page 30: Read Status

    ST7038 Read Status BF: Busy Flag When BF is “H”, it indicates that the internal operation is processing. So the next instruction(s) cannot be accepted until BF=”L”. Be sure to check BF bit before issuing next instruction. In serial interface mode (including I C mode), please use delay to avoid the next instruction conflict with the internal operation.
  • Page 31 ST7038 S/C: Selects Cursor or Screen to perform the shift function. S/C=”H”: The Screen (current display) is selected to shift. The direction is controlled by R/L bit; S/C=”L”: The Cursor is selected to shift. The direction is controlled by R/L bit. R/L: Selects the shift direction.
  • Page 32 ST7038 V0 Control 1 & 2 V0 Control 1 V0 Control 2 PD: Set Power Down Mode ON/OFF. PD=”H”: Enter Power Down Mode; PD=”L”: Exit Power Down Mode. VC[6:0]: Set V0 voltage. Please refer to “POWER SUPPLY FOR LCD ” section for more detailed information. V0 (V) 2.000 2.024...
  • Page 33 ST7038 Instruction Table 2, IS[1:0]=(1,0) Set Display Mode UD: Select double height font display position on screen. This bit is only valid when N2=0, N1=1 and DH=1. UD=”H”: Double height font is displayed on COM1~COM16; UD=”L”: Double height font is displayed on COM9~COM24. DH=0, N2=1 &...
  • Page 34 ST7038 For example, the normal height font and the doubled height font are shown as below. 2 line mode normal display (DH=0, N2=0, N1=1) 1 line mode with double height font (DH=1, N2=0, N1=0) N[2,1]: Control the “Display Line Number”. ST7038 has 17-common and 100-segment LCD driving signals as default.
  • Page 35 ST7038 SHLS: (Pin definition is NOT changed when SHLS=0) SHLS=1: SEG1~100 ←Column address 0~99 (Normal) SHLS=0: SEG100~1 ←Column address 99~0 (Invert) * Pin definition of SEG is NOT changed when SHLS=0 * 3-Line Display Mode uses only 80 segments. SHLC: (Pin definition is changed when SHLC=0) SHLC=1: COM1~24 ←Row address 0~23 (Normal) SHLC=0: COM1~24...
  • Page 36: Mpu Interface

    ST7038 MPU INTERFACE The ST7038 supports various kinds of MPU interface to communicate with MPU: Parallel 4-bit 6800/8080-series, Parallel 8-bit 6800/8080-series, Serial 3/4-Line SPI and I C operation. The following figures are referential circuits connected with different kinds of MPU. The microprocessor interface pins (CSB, /WR, /RD, A0 and D7~D0) should not be left floating in any operation mode.
  • Page 37 ST7038 Intel 8051 interface: Serial 4-line SPI Intel 8051 interface: Serial 3-line SPI Intel 8051 interface: Serial I Ver 1.1 37/61 2007/01/25...
  • Page 38 ST7038 INITIALIZATION Initial Flow POWER ON and external reset Wait time >40mS After VDD stable Contrast set Function set R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VC3 VC2 VC1 VC0 Wait time >32.4μS Wait time >32.4μS Power/Contrast Set...
  • Page 39 ST7038 Initial Code (8051 MPU, Parallel 8-bit Interface) ;--------------------------------------------------------------------------------- P1,#FFH ;For Check Busy Flag INITIAL_START: CALL HARDWARE_RESET ;--------------------------------------------------------------------------------- CALL DELAY40mS CHK_BUSY: ;Check Busy Flag A,#32H ;FUNCTION SET CALL WRINS_NOCHK ;8 bit, SETB CALL DELAY40uS SETB A,#32H ;FUNCTION SET P1.7,$ CALL WRINS_NOCHK ;8 bit, CALL...
  • Page 40 ST7038 Initial Code (8051 MPU, Serial 4-line SPI Interface) ;------------------------------------------------------------------- PUSH INITIAL_START: A,#F0H INITIAL_START: ;EX:Port 3.0 CALL HARDWARE_RESET ;EX:Port 3.1 CALL DELAY40mS SETB ;EX:Port 3.2 A,#22H ;FUNCTION SET P1,A ;EX:Port1=Data Bus CALL WRINS_NOCHK ;8 bit, CALL DELAY40uS A,#22H ;FUNCTION SET SWAP CALL WRINS_NOCHK...
  • Page 41 ST7038 Initial Code (8051 MPU, Parallel 4-bit Interface) ;--------------------------------------------------------------------------------- INITIAL_START: SI,C CALL HARDWARE_RESET CALL DELAY40mS A,#32H ;FUNCTION SET CALL WRINS_NOCHK ;8 bit, DJNZ R1,$1 CALL DELAY40uS A,#32H ;FUNCTION SET CALL WRINS_NOCHK ;8 bit, CALL DLY1.5mS CALL DELAY40uS A,#54H ;Internal OSC frequency adjustment CALL WRINS_NOCHK...
  • Page 42 ST7038 LCD & ST7038 CONNECTION SHLC/SHLS bits can select different scan direction for LCD panel. 1 & 2-Line Display Mode COM normal direction, SEG normal direction (SHLC=1, SHLS=1) COM normal direction, SEG reverse direction (SHLC=1, SHLS=0) COM reverse direction, SEG normal direction (SHLC=0, SHLS=1) COM reverse direction, SEG reverse direction (SHLC=0, SHLS=0) 3-Line Display Mode...
  • Page 43 ST7038 COM reverse direction, SEG normal direction (SHLC=0, SHLS=1) 3 line x 16 characters, SHLC=0, SHLS=1 COM reverse direction, SEG reverse direction (SHLC=0, SHLS=0) 3 line x 16 characters, SHLC=0, SHLS=0 Ver 1.1 43/61 2007/01/25...
  • Page 44 ST7038 POWER SUPPLY FOR LCD DRIVER Built-in Booster circuit: The voltage booster uses analog power (V ) to generate boosted voltage. The boost stage is controlled by hardware connection. Please refer to the following figure for the detailed booster circuit connection. Built-in Regulator circuit: The built-in Regulator circuit is shown below, where the Vref = 1.47V.
  • Page 45 ST7038 Built-in Follower circuit: There are 3 kinds of built-in Follower circuits. By instruction, the follower can be configured to be: OPF[2:1] Description (0,0) Select built-in Follower (0,1) Select built-in bias resistor (9.9K) (1,0) Select built-in bias resistor (3.3K) (1,1) Select external bias circuit (built-in Follower is OFF) Note: When using built-in bias resistors (9.9K or 3.3K), the current consumption maybe larger than using built-in Follower.
  • Page 46: Absolute Limiting Values

    ST7038 ABSOLUTE LIMITING VALUES is 0V unless otherwise specified. Characteristics Symbol Value Unit Digital Power Supply Voltage -0.3 ~ 3.6 Analog Power Supply Voltage -0.3 ~ 3.6 Interface Input Voltage -0.3 ~ V +0.5 Apply on : CSB, RESB, A0, /WR, /RD, D7~D0 LCD Driver Voltage (Booster &...
  • Page 47 ST7038 DC CHARACTERISTICS is 0V unless otherwise specified. Characteristics Symbol Test Condition Min. Typ. Max. Unit Operating Voltage 1.65 LCD Voltage V0-Vss 12.0 =3.0V * Power Supply Current (use internal power circuit) =3.0V Sleep Mode (use internal power circuit) Input High Voltage 0.8 V (Except OSC1) Input Low Voltage...
  • Page 48 ST7038 AC CHARACTERISTICS 6800 Interface Ta = -30 ~ 85 VDD=1.8V VDD=2.5V VDD=3.3V Item Signal Symbol Units Min. Max. Min. Max. Min. Max. Address hold time Address setup time System cycle time CYC6 Data setup time Data hold time D0 to D7 Access time ACC6 Output disable time...
  • Page 49 ST7038 8080 Interface Ta = -30 ~ 85 Item VDD=1.8V VDD=2.5V VDD=3.3V Signal Symbol Units Min. Max. Min. Max. Min. Max. Address hold time Address setup time System cycle time CYC8 Enable L pulse width (WRITE) CCLW Enable H pulse width (WRITE) CCHW D0 to D7 Enable L pulse width (READ)
  • Page 50 ST7038 Serial 4-Line Interface Ta = -30 ~ 85 VDD=1.8V VDD=2.5V VDD=3.3V Item Signal Symbol Units Min. Max. Min. Max. Min. Max. Serial Clock Period SCYC SCL “H” pulse width SCL “L” pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time...
  • Page 51 ST7038 Serial 3-Line Interface Ta = -30 ~ 85 VDD=1.8V VDD=2.5V VDD=3.3V Item Signal Symbol Units Min. Max. Min. Max. Min. Max. Serial Clock Period SCYC SCL “H” pulse width SCL “L” pulse width Data setup time Data hold time CS-SCL time Note: All timing is specified using 20% and 80% of VDD as the reference.
  • Page 52 ST7038 Serial I C Interface Ta = -30 ~ 85 VDD=1.8V VDD=2.5V VDD=3.3V Symb Conditio Rating Rating Rating Item Signal Units Min. Max. Min. Max. Min. Max. SCL clock frequency SCLK — SCL clock low period — — — — —...
  • Page 53 ST7038 Hardware Reset (XRESET) Ver 1.1 53/61 2007/01/25...
  • Page 54 ST7038 LCD FRAME RATE 1-Line Display Mode: Assume the oscillation frequency is 284KHz (1 clock cycle time = 3.52us), 1/4 bias, 1/9 duty, 1 frame = 14.08ms = 71Hz (SHLC=1, SHLS=1). COM1 V2 / V3 COM2 V2 / V3 COMI V2 / V3 SEGx V2 / V3...
  • Page 55 ST7038 2-Line or 1-Line Double Height Display Mode: Assume the oscillation frequency is 249.7KHz (1 clock cycle time = 4us), 1/5 bias, 1/17 duty, 1 frame = 14.42ms = 69.36Hz (SHLC=1, SHLS=1). COM1 COM2 COMI SEGx SEGx 1 Frame Ver 1.1 55/61 2007/01/25...
  • Page 56 ST7038 3-Line or 2-Line Double Height Display Mode: Assume the oscillation frequency is 370.5KHz (1 clock cycle time = 2.70us), 1/6 bias, 1/25 duty, 1 frame = 14.04ms = 71.25Hz (SHLC=1, SHLS=1). COM1 COM2 COMI SEGx SEGx 1 Frame Ver 1.1 56/61 2007/01/25...
  • Page 57 ST7038 I/O PAD CONFIGURATION PMOS NMOS Input PAD (No Pull up): RS, R/W, XRESET, CSB, Enable PMOS PMOS PMOS Data NMOS NMOS I/O PAD: DB0-DB7 Ver 1.1 57/61 2007/01/25...
  • Page 58: Application Circuit

    ST7038 APPLICATION CIRCUIT 6800 series 8-bit Interface: Ver 1.1 58/61 2007/01/25...
  • Page 59 ST7038 8080 series 8-bit Interface: Ver 1.1 59/61 2007/01/25...
  • Page 60 ST7038 C Interface: Ver 1.1 60/61 2007/01/25...
  • Page 61: Reversion History

    ST7038 Reversion History Version Date Description 2006/08/03 Release Version Modify minimum operation VDD range to 1.65V. 2007/01/25 Remove reversion history before Ver 1.0. Redraw Timing Figures. Ver 1.1 61/61 2007/01/25...

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