Table 124. Fsmc_Btrx Bit Fields - ST STM32F101 series Reference Manual

Flexible static memory controller (FSMC)
Bit No.
1
0
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
WAIT management in asynchronous accesses
If the asynchronous memory asserts a WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase) programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase (DATAST in FSMC_BTRx register) must be programmed so that the
WAIT signal meets the following conditions:
•
For read accesses: WAIT can be detected 4 HCLK cycles before data is being sampled
or 6 HCLK cycles before NOE is deasserted (refer to
during a read
•
For write accesses: WAIT can be detected 4 HCLK cycles before NWE deassertion
(refer to
523/1128
Table 123. FSMC_BCRx bit fields (continued)
Bit name
MUXEN 0x1
MBKEN 0x1

Table 124. FSMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
Duration of the last phase of the access (BUSTURN+1 HCLK)
BUSTURN
Duration of the second access phase (DATAST+3 HCLK cycles for
DATAST read accesses and DATAST+1 HCLK cycles for write accesses).
This value cannot be 0 (minimum is 1)
Duration of the middle phase of the access (ADDHLD+1 HCLK
ADDHLD
cycles).This value cannot be 0 (minimum is 1).
ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles).
access).
Figure 200: Asynchronous wait during a write
DocID13902 Rev 15
Value to set
Value to set
Figure 199: Asynchronous wait
access).
RM0008