Can Mailbox Registers; Figure 236. Rx And Tx Mailboxes - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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Controller area network (bxCAN)

Bits 19:16 TS1[3:0]

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:0 BRP[9:0]

CAN mailbox registers

This chapter describes the registers of the transmit and receive mailboxes. Refer to

Section 24.7.5: Message storage on page 659

Transmit and receive mailboxes have the same registers except:

The FMI field in the CAN_RDTxR register.

A receive mailbox is always write protected.

A transmit mailbox is write-enabled only while empty, corresponding TME bit in the

CAN_TSR register set.

There are 3 TX Mailboxes and 2 RX Mailboxes. Each RX Mailbox allows access to a 3 level

depth FIFO, the access being offered only to the oldest received message in the FIFO.

Each mailbox consist of 4 registers.

Time segment 1

These bits define the number of time quanta in Time Segment 1

x (TS1[3:0] + 1)

For more information on bit timing, please refer to

Baud rate prescaler

These bits define the length of a time quanta.

= (BRP[9:0]+1) x t

for detailed register mapping.

DocID13902 Rev 15

Section 24.7.7: Bit timing on page

Three Tx Mailboxes

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