Dynamic Update Of The Otg_Fs_Hfir Register; Usb Data Fifos; Figure 307. Updating Otg_Fs_Hfir Dynamically - ST STM32F101 series Reference Manual

RM0008
To save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS
core.
28.9

Dynamic update of the OTG_FS_HFIR register

The USB core embeds a dynamic trimming capability of micro-SOF framing period in host
mode allowing to synchronize an external device with the micro-SOF frames.
When the OTG_HS_HFIR register is changed within a current micro-SOF frame, the SOF
period correction is applied in the next frame as described in
28.10

USB data FIFOs

The USB system features 1.25 Kbyte of dedicated RAM with a sophisticated FIFO control
mechanism. The packet FIFO controller module in the OTG_FS core organizes RAM space
into Tx-FIFOs into which the application pushes the data to be temporarily stored before the
USB transmission, and into a single Rx FIFO where the data received from the USB are
temporarily stored before retrieval (popped) by the application. The number of instructed
FIFOs and how these are organized inside the RAM depends on the device's role. In
peripheral mode an additional Tx-FIFO is instructed for each active IN endpoint. Any FIFO
size is software configured to better meet the application requirements.

Figure 307. Updating OTG_FS_HFIR dynamically

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USB on-the-go full-speed (OTG_FS)
Figure 307.
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