RM0008
Ethernet (ETH): media access control (MAC) with DMA controller
Figure 338. Transmission bit order
LSB
MSB
D0
D1
Bibit stream
LSB
D0
D1
MII_TXD[3:0]
D2
MSB
D3
Nibble stream
ai15632
MII/RMII transmit timing diagrams
Figure 339. Transmission with no collision
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
PR
EA
MB
LE
MII_CS
MII_COL
Low
ai15631
DocID13902 Rev 15
980/1128
1064
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