Figure 11. Clock Tree - ST STM32F101 series Reference Manual

RM0008
ETH_MII_TX_CLK
ETH_MII_RX_CLK
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. For full details about the internal and external clock source characteristics, please refer to the "Electrical
characteristics" section in your device datasheet.
The advanced clock controller features 3 PLLs to provide a high degree of flexibility to the
application in the choice of the external crystal or oscillator to run the core and peripherals at
the highest frequency and guarantee the appropriate frequency for the Ethernet and USB
OTG FS.
A single 25 MHz crystal can clock the entire system and all peripherals including the
Ethernet and USB OTG FS peripherals. In order to achieve high-quality audio performance,
an audio crystal can be used. In this case, the I2S master clock can generate all standard
sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy.
For more details about clock configuration for applications requiring Ethernet, USB OTG FS
2
and/or I
connectivity line device datasheet.
40 kHz
LSI
RC
LSI
OSC32_IN
32.768 kHz
LSE
LSE
OSC32_OUT
OSC
/128
RTCSEL[1:0]
to Flash prog. IF
XT1 to MCO
8 MHz
HSI RC
3-25 MHz
OSC_IN
HSE
/1,2,3....
OSC_OUT
OSC
..../15, /16
PREDIV1
PREDIV1SCR
PREDIV2
/1,2,3....
..../15, /16
MCO[3:0]
HSE
HSI
MCO
PLLCLK/2
PLL2CLK
PLL3CLK/2
PLL3CLK
XT1
SYSCLK
72 MHz max.
(see note1)
Ethernet
PHY
/2, /20
S (audio), please refer to "Appendix A Applicative block diagrams" in your
Connectivity line devices: reset and clock control (RCC)

Figure 11. Clock tree

to independent watchdog
IWDGCLK
to RTC
RTCCLK
CSS
HSE
FLITFCLK
HSI
PLLMUL
/2
PLLCLK
x4, x5,... x9,
x6.5
SW
PLLVCO (2 × PLLCLK)
PLLSCR
USB prescaler
/2,3
OTGFSCLK
PLL2MUL
48 MHz
to USB OTG FS
x8, x9,... x14,
x16, x20
to I2S2 interface
PLL2CLK
PLL3MUL
to MCO
to I2S3 interface
PLL3VCO
x8, x9,... x14,
(2 × PLL3CLK)
x16, x20
PLL3CLK to MCO
APB1 prescaler
/1, 2, 4, 8, 16
AHB prescaler
/1,/2 ../512
APB2 prescaler
/1, 2, 4, 8, 16
MACTXCLK
MII_RMII_SEL
in AFIO_MAPR
to Ethernet MAC
MACRXCLK
MACRMIICLK
DocID13902 Rev 15
SYSCLK
system clock
HCLK to AHB bus, core memory and DMA
/8
to Cortex System timer
FCLK Cortex free running clock
36 MHz max
PCLK1
Peripheral clock enable
to APB1 peripherals
to TIM2,3,4,5,
TIM2,3,4,5,6,7
6 & 7
If(APB1 prescaler =1) x1
else x2 TIMxCLK
Peripheral clock enable
72 MHz max
PCLK2
Peripheral clock enable
to APB2 peripherals
TIM1
to TIM1
If(APB2 prescaler =1) x1
else x2
TIMxCLK
Peripheral clock enable
ADC prescaler ADCCLK
to ADC1,2
/2, 4, 6, 8
14 MHz max
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