Arbiter; Dma Channels - ST STM32F101 series Reference Manual

RM0008
In summary, each DMA transfer consists of three operations:
•
The loading of data from the peripheral data register or a location in memory addressed
through an internal current peripheral/memory address register. The start address used
for the first transfer is the base peripheral/memory address programmed in the
DMA_CPARx or DMA_CMARx register
•
The storage of the data loaded to the peripheral data register or a location in memory
addressed through an internal current peripheral/memory address register. The start
address used for the first transfer is the base peripheral/memory address programmed
in the DMA_CPARx or DMA_CMARx register
•
The post-decrementing of the DMA_CNDTRx register, which contains the number of
transactions that have still to be performed.
13.3.2

Arbiter

The arbiter manages the channel requests based on their priority and launches the
peripheral/memory access sequences.
The priorities are managed in two stages:
•
Software: each channel priority can be configured in the DMA_CCRx register. There
are four levels:
–
–
–
–
•
Hardware: if 2 requests have the same software priority level, the channel with the
lowest number will get priority versus the channel with the highest number. For
example, channel 2 gets priority over channel 4.
Note: In high-density, XL-density and connectivity line devices, the DMA1 controller has priority
over the DMA2 controller.
13.3.3

DMA channels

Each channel can handle DMA transfer between a peripheral register located at a fixed
address and a memory address. The amount of data to be transferred (up to 65535) is
programmable. The register which contains the amount of data items to be transferred is
decremented after each transaction.
Programmable data sizes
Transfer data sizes of the peripheral and memory are fully programmable through the
PSIZE and MSIZE bits in the DMA_CCRx register.
Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented after
each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If
incremented mode is enabled, the address of the next transfer will be the address of the
previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer
address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During
transfer operations, these registers keep the initially programmed value. The current
Very high priority
High priority
Medium priority
Low priority
DocID13902 Rev 15
Direct memory access controller (DMA)
276/1128
291