Clock Interrupt Register (Rcc_Cir) - ST STM32F101 series Reference Manual

RM0008
7.3.3

Clock interrupt register (RCC_CIR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
15 14 13
PLL
RDYIE
Reserved
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
Bits 22:21
Bit 20 PLLRDYC: PLL ready interrupt clear
Bit 19 HSERDYC: HSE ready interrupt clear
Bit 18 HSIRDYC: HSI ready interrupt clear
Bit 17 LSERDYC: LSE ready interrupt clear
Bit 16 LSIRDYC: LSI ready interrupt clear
Bits 15:13
Bit 12 PLLRDYIE: PLL ready interrupt enable
Low-, medium-, high- and XL-density reset and clock control (RCC)
28 27 26 25
Reserved
12 11 10 9
HSE HSI LSE
RDYIE RDYIE RDYIE
rw rw rw rw
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Reserved, must be kept at reset value.
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
Reserved, must be kept at reset value.
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
DocID13902 Rev 15
24 23 22 21
CSSC
Reserved
w
8 7 6 5
LSI
CSSF
RDYIE
Reserved
rw r
20 19 18 17
PLL HSE HSI LSE
RDYC RDYC RDYC RDYC
w w w w
4 3 2 1
PLL HSE HSI LSE
RDYF RDYF RDYF RDYF
r r r r
16
LSI
RDYC
w
0
LSI
RDYF
r
104/1128
122