Ahb Peripheral Clock Reset Register (Rcc_Ahbrstr) - ST STM32F101 series Reference Manual

Connectivity line devices: reset and clock control (RCC)
Bit 24 RMVF: Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 23:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low speed oscillator ready
Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 internal 40 kHz RC oscillator clock
cycles.
0: Internal RC 40 kHz oscillator not ready
1: Internal RC 40 kHz oscillator ready
Bit 0 LSION: Internal low speed oscillator enable
Set and cleared by software.
0: Internal RC 40 kHz oscillator OFF
1: Internal RC 40 kHz oscillator ON
8.3.11

AHB peripheral clock reset register (RCC_AHBRSTR)

Address offset: 0x28
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
15 14 13
ETHMAC
RST
Res. Res.
rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 ETHMACRST Ethernet MAC reset
Bit 13
Bit 12 OTGFSRST USB OTG FS reset
Bits 11:0 Reserved, must be kept at reset value.
153/1128
28 27 26
12 11 10
OTGFSR
ST
rw
Set and cleared by software.
0: No effect
1: Reset ETHERNET MAC
Reserved, must be kept at reset value.
Set and cleared by software.
0: No effect
1: Reset USB OTG FS
25 24 23 22
Reserved
9 8 7 6
Reserved
DocID13902 Rev 15
21 20 19 18
5 4 3 2
RM0008
17 16
1 0