Timer Synchronization (Tim9/12); Debug Mode; Tim9 And Tim12 Registers; Tim9/12 Control Register 1 (Timx_Cr1) - ST STM32F101 series Reference Manual

General-purpose timers (TIM9 to TIM14)
16.3.12

Timer synchronization (TIM9/12)

The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 15.3.15: Timer synchronization on page 391
16.3.13

Debug mode

When the microcontroller enters debug mode (Cortex
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to
watchdog, bxCAN and
16.4

TIM9 and TIM12 registers

Refer to
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
16.4.1

TIM9/12 control register 1 (TIMx_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Reserved
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
437/1128
I2C.
Section 2.1 on page 47
12 11 10 9
CKD[1:0]
rw
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: t = t
DTS CK_INT
01: t = 2 × t
DTS CK_INT
10: t = 4 × t
DTS CK_INT
11: Reserved
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
0: Counter is not stopped on the update event
1: Counter stops counting on the next update event (clearing the CEN bit).
Section 31.16.2: Debug support for timers,
for a list of abbreviations used in register descriptions.
8 7 6
ARPE
rw rw
DocID13902 Rev 15
for details.
®
-M3 core halted), the TIMx counter
5 4 3
OPM URS
Reserved
rw
RM0008
2 1 0
UDIS CEN
rw rw rw