Figure 167. Control Circuit In Gated Mode; Figure 168. Control Circuit In Trigger Mode - ST STM32F101 series Reference Manual

RM0008
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don't need any filter, so we keep IC2F='0000'). The capture
prescaler is not used for triggering, so you don't need to configure it. The CC2S bits are
configured to select the input capture source only, CC2S='01' in TIMx_CCMR1 register.
Program CC2P='1' and CC2NP='0' in TIMx_CCER register to validate the polarity (and
detect low level only).
2. Configure the timer in trigger mode by writing SMS='110' in TIMx_SMCR register.
Select TI2 as the input source by writing TS='110' in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 167. Control circuit in gated mode

TI1
cnt_en
Counter clock = ck_cnt = ck_psc
Counter register
TIF

Figure 168. Control circuit in trigger mode

TI2
cnt_en
Counter clock = ck_cnt = ck_psc
Counter register
TIF
DocID13902 Rev 15
General-purpose timers (TIM9 to TIM14)
30 31 32 33 34
Write TIF=0
34
35 36 37 38
35 36 37 38
436/1128
460