Rcc Register Map; Table 19. Rcc Register Map And Reset Values - ST STM32F101 series Reference Manual

RM0008
Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor
Set and cleared by software to select PREDIV1 division factor. These bits can be written only
when PLL is disabled.
Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the
0000: PREDIV1 input clock not divided
0001: PREDIV1 input clock divided by 2
0010: PREDIV1 input clock divided by 3
0011: PREDIV1 input clock divided by 4
0100: PREDIV1 input clock divided by 5
0101: PREDIV1 input clock divided by 6
0110: PREDIV1 input clock divided by 7
0111: PREDIV1 input clock divided by 8
1000: PREDIV1 input clock divided by 9
1001: PREDIV1 input clock divided by 10
1010: PREDIV1 input clock divided by 11
1011: PREDIV1 input clock divided by 12
1100: PREDIV1 input clock divided by 13
1101: PREDIV1 input clock divided by 14
1110: PREDIV1 input clock divided by 15
1111: PREDIV1 input clock divided by 16
8.3.13

RCC register map

The following table gives the RCC register map and the reset values.
Offset Register
RCC_CR
0x000
Reset value
RCC_CFGR
0x004
Reset value
RCC_CIR
0x008
Reset value
RCC_CFGR register changes Bit(0) accordingly.

Table 19. RCC register map and reset values

Rese
rved
0 0 0 0 0 0
MCO [3:0]
Reserved
0 0 0 0
Reserved
0 0 0 0 0 0 0 0
DocID13902 Rev 15
Connectivity line devices: reset and clock control (RCC)
Reserved
0 0 0 0 x x x x x x x x 1 0 0 0 0
ADC
PLLMUL
PRE
[3:0]
[1:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HSICAL[7:0] HSITRIM[4:0]
PPRE2 PPRE1
HPRE[3:0]
[2:0] [2:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1
SWS SW
[1:0] [1:0]
156/1128
158