Nand Flash Operations; Figure 204. Nand/Pc Card Controller Timing For Common Memory Access - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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1. NOE remains high (inactive) during write access. NWE remains high (inactive) during read access.

2. NCEx goes low as soon as NAND access is requested and remains low until a different memory bank is

NAND Flash operations

The command latch enable (CLE) and address latch enable (ALE) signals of the NAND

Flash device are driven by some address signals of the FSMC controller. This means that to

send a command or an address to the NAND Flash memory, the CPU has to perform a write

to a certain address in its memory space.

A typical page read operation from the NAND Flash device is as follows:

Program and enable the corresponding memory bank by configuring the FSMC_PCRx

and FSMC_PMEMx (and for some devices, FSMC_PATTx, see

Flash pre-wait functionality on page

the NAND Flash (PWID bits for the databus width of the NAND Flash, PTYP = 1,

PWAITEN = 0 or 1 as needed, see section

(FSMC_PMEM2..4) on page 549

The CPU performs a byte write in the common memory space, with data byte equal to

one Flash command byte (for example 0x00 for Samsung NAND Flash devices). The

CLE input of the NAND Flash is active during the write strobe (low pulse on NWE), thus

the written byte is interpreted as a command by the NAND Flash. Once the command

is latched by the NAND Flash device, it does not need to be written for the following

page read operations.

The CPU can send the start address (STARTAD) for a read operation by writing the

required bytes (for example four bytes or three for smaller capacity devices),

STARTAD[7:0], STARTAD[15:8], STARTAD[23:16] and finally STARTAD[25:24] for

64 Mb x 8 bit NAND Flash) in the common memory or attribute space. The ALE input of

DocID13902 Rev 15

Flexible static memory controller (FSMC)

MEMxWAIT + 1

543) registers according to the characteristics of

Common memory space timing register 2..4

for timing configuration).

MEMxHOLD + 1

Section 21.6.5: NAND