Spi Data Register (Spi_Dr) - ST STM32F101 series Reference Manual

Serial peripheral interface (SPI)
Bit 3 UDR: Underrun flag
0: No underrun occurred
1: Underrun occurred
Note: This bit is not used in SPI mode.
Bit 2 CHSIDE: Channel side
0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
Note: This bit is not used for SPI mode and is meaningless in PCM mode.
Bit 1 TXE: Transmit buffer empty
Bit 0 RXNE: Receive buffer not empty
25.5.4

SPI data register (SPI_DR)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
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Bits 15:0 DR[15:0]: Data register
Note: These notes apply to SPI mode:
737/1128
This flag is set by hardware and reset by a software sequence. Refer to
page 731 for the software sequence.
0: Tx buffer not empty
1: Tx buffer empty
0: Rx buffer empty
1: Rx buffer not empty
12 11 10 9
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Data received or to be transmitted.
The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for
reading (Receive buffer). A write to the data register will write into the Tx buffer and a read
from the data register will return the value held in the Rx buffer.
Depending on the data frame format selection bit (DFF in SPI_CR1 register), the data
sent or received is either 8-bit or 16-bit. This selection has to be made before enabling
the SPI to ensure correct operation.
For an 8-bit data frame, the buffers are 8-bit and only the LSB of the register
(SPI_DR[7:0]) is used for transmission/reception. When in reception mode, the MSB of
the register (SPI_DR[15:8]) is forced to 0.
For a 16-bit data frame, the buffers are 16-bit and the entire register, SPI_DR[15:0] is
used for transmission/reception.
8 7 6
DR[15:0]
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DocID13902 Rev 15
Section 25.4.7 on
5 4 3 2
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RM0008
1 0
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