I 2 C Main Features - ST STM32F101 series Reference Manual

RM0008
2
26.2 I C main features
• Parallel-bus/I
•
Multimaster capability: the same interface can act as Master or Slave
2
• I C Master features:
–
–
2
•
I C Slave features:
–
–
–
•
Generation and detection of 7-bit/10-bit addressing and General Call
•
Supports different communication speeds:
–
–
•
Analog noise filter
•
Status flags:
–
–
–
•
Error flags:
–
–
–
–
•
2 Interrupt vectors:
–
–
•
Optional clock stretching
•
1-byte buffer with DMA capability
•
Configurable PEC (packet error checking) generation or verification:
–
–
•
SMBus 2.0 Compatibility:
–
–
–
–
–
• PMBus Compatibility
Note: Some of the above features may not be available in certain products. The user should refer
to the product data sheet, to identify the specific features supported by the I
implementation.
2
C protocol converter
Clock generation
Start and Stop generation
2
Programmable I C Address detection
Dual Addressing Capability to acknowledge 2 slave addresses
Stop bit detection
Standard Speed (up to 100 kHz)
Fast Speed (up to 400 kHz)
Transmitter/Receiver mode flag
End-of-Byte transmission flag
2
I C busy flag
Arbitration lost condition for master mode
Acknowledgment failure after address/ data transmission
Detection of misplaced start or stop condition
Overrun/Underrun if clock stretching is disabled
1 Interrupt for successful address/ data communication
1 Interrupt for error condition
PEC value can be transmitted as last byte in Tx mode
PEC error checking for last received byte
25 ms clock low timeout delay
10 ms master cumulative clock low extend time
25 ms slave cumulative clock low extend time
Hardware PEC generation/verification with ACK control
Address Resolution Protocol (ARP) supported
DocID13902 Rev 15
Inter-integrated circuit (I
2
C) interface
2
C interface
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