RM0008
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
read CCR1H
read CCR1L
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
Figure 126. Capture/compare channel 1 main circuit
S
read_in_progress
Capture/Compare Preload Register
R
capture_transfer
input
mode
Capture/Compare Shadow Register
Figure 127. Output stage of capture/compare channel (channel 1)
DocID13902 Rev 15
General-purpose timers (TIM2 to TIM5)
APB Bus
MCU-peripheral interface
8
8
compare_transfer
capture
Counter
write CCR1H
S
write_in_progress
write CCR1L
R
CC1S[1]
output
mode
CC1S[0]
UEV
(from time
comparator
base unit)
CNT>CCR1
CNT=CCR1
OC1PE
OC1PE
TIMx_CCMR1
376/1128
417
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