Table 122. Fsmc_Bwtrx Bit Fields; Figure 197. Multiplexed Read Accesses - ST STM32F101 series Reference Manual

Flexible static memory controller (FSMC)
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Muxed mode - multiplexed asynchronous access to NOR Flash memory
1. The bus turnaround delay (BUSTURN + 1) and the delay between side-by-side transactions overlap, so
BUSTURN ≤ 5 has not impact.
521/1128

Table 122. FSMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x3
DATLAT 0x0
CLKDIV 0x0
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+3 HCLK cycles) for
DATAST
write accesses. This value cannot be 0 (minimum is 1)
Duration of the middle phase of the write access (ADDHLD+1 HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET+1 HCLK cycles) for
ADDSET
write accesses.

Figure 197. Multiplexed read accesses

A[25:16]
NADV
NEx
NOE
NWE
High
AD[15:0]
Lower address
(ADDSET +1)
HCLK cycles
DocID13902 Rev 15
Value to set
Memory transaction
data driven
by memory
1HCLK cycle
(DATAST + 1) 2 HCLK
cycles
HCLK cycles
(ADDHLD + 1)
HCLK cycles
Data sampled
(1)
(BUSTURN + 1)
HCLK cycles
Data strobe
ai14728c
RM0008