Serial Peripheral Interface (Spi); Spi Introduction - ST STM32F101 series Reference Manual

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25

Serial peripheral interface (SPI)

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
25.1

SPI introduction

In high-density, XL-density and connectivity line devices, the SPI interface provides two
main functions, supporting either the SPI protocol or the I
the SPI function that is selected. It is possible to switch the interface from SPI to I
software.
In Cat.1 and Cat.2 devices, the I
The serial peripheral interface (SPI) allows half/ full-duplex, synchronous, serial
communication with external devices. The interface can be configured as the master and in
this case it provides the communication clock (SCK) to the external slave device. The
interface is also capable of operating in multimaster configuration.
It may be used for a variety of purposes, including simplex synchronous transfers on two
lines with a possible bidirectional data line or reliable communication using CRC checking.
2
The I S is also a synchronous serial communication interface. It can address four different
audio standards including the I
and the PCM standard. It can operate as a slave or a master device in full-duplex mode
(using 4 pins) or in half-duplex mode (using 6 pins). Master clock can be provided by the
interface to an external slave component when the I
master.
Warning:
2
S protocol is not available.
2
S Philips standard, the MSB- and LSB-justified standards,
Since some SPI3/I2S3 pins are shared with JTAG pins
(SPI3_NSS/I2S3_WS with JTDI and SPI3_SCK/I2S3_CK with
JTDO), they are not controlled by the IO controller and are
reserved for JTAG usage (after each Reset).
For this purpose, prior to configure the SPI3/I2S3 pins, the
user has to disable the JTAG and use the SWD interface
(when debugging the application), or disable both JTAG/SWD
interfaces (for standalone applications). For more
information on the configuration of JTAG/SWD interface pins,
please refer to Section 9.3.5: JTAG/SWD alternate function
remapping.
DocID13902 Rev 15
Serial peripheral interface (SPI)
2
S audio protocol. By default, it is
2
S is configured as the communication
2
S by
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