Table 210. Clock Range; Figure 329. Mdio Timing And Frame Structure - Read Cycle - ST STM32F101 series Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
SMI read operation
When the user sets the MII Busy bit in the Ethernet MAC MII address register
(ETH_MACMIIAR) with the MII Write bit at 0, the SMI initiates a read operation in the PHY
registers by transferring the PHY address and the register address in PHY. The application
should not change the MII Address register contents or the MII Data register while the
transaction is ongoing. Write operations to the MII Address register or MII Data Register
during this period are ignored (the Busy bit is high) and the transaction is completed without
any error. After the read operation has completed, the SMI resets the Busy bit and then
updates the MII Data register with the data read from the PHY.
Figure 329
MDC
MDIO
SMI clock selection
The MAC initiates the Management Write/Read operation. The SMI clock is a divided clock
whose source is the application clock (AHB clock). The divide factor depends on the clock
range setting in the MII Address register.
Table 210
0100, 0101, 0110, 0111
965/1128
shows the frame format for the read operation.

Figure 329. MDIO timing and frame structure - Read cycle

32 1's 0 1 1 0
A4 A3 A2 A1 A0 R4 R3
Start
OP
Preamble
of
code
frame
Data to PHY
shows how to set the clock ranges.
Selection
0000
0001
0010
0011
DocID13902 Rev 15
R2 R1 R0
Register address Turn
PHY address

Table 210. Clock range

HCLK clock
60-72 MHz
Reserved
20-35 MHz
35-60 MHz
Reserved
D15 D14 D1 D0
data
around
Data from PHY
MDC clock
AHB clock / 42
-
AHB clock / 16
AHB clock / 26
-
RM0008
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