Af Remap And Debug I/O Configuration Register2 (Afio_Mapr2) - ST STM32F101 series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.4.7

AF remap and debug I/O configuration register2 (AFIO_MAPR2)

Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29
15 14 13
Reserved
Bits 31:11
Bit 10 FSMC_NADV: NADV connect/disconnect
Bit 9 TIM14_REMAP: TIM14 remapping
Bit 8 TIM13_REMAP: TIM13 remapping
Bit 7 TIM11_REMAP: TIM11 remapping
Bit 6 TIM10_REMAP: TIM10 remapping
Bit 5 TIM9_REMAP: TIM9 remapping
Bits 4:0
193/1128
28 27 26 25
12 11 10 9
FSM
TIM14_
C_NA
REMA
DV
P
rw rw
Reserved.
This bit is set and cleared by software. It controls the use of the optional FSMC_NADV
signal.
0: The NADV signal is connected to the output (default)
1: The NADV signal is not connected. The I/O pin can be used by another peripheral.
This bit is set and cleared by software. It controls the mapping of the TIM14_CH1 alternate
function onto the GPIO ports.
0: No remap (PA7)
1: Remap (PF9)
This bit is set and cleared by software. It controls the mapping of the TIM13_CH1 alternate
function onto the GPIO ports.
0: No remap (PA6)
1: Remap (PF8)
This bit is set and cleared by software. It controls the mapping of the TIM11_CH1 alternate
function onto the GPIO ports.
0: No remap (PB9)
1: Remap (PF7)
This bit is set and cleared by software. It controls the mapping of the TIM10_CH1 alternate
function onto the GPIO ports.
0: No remap (PB8)
1: Remap (PF6)
This bit is set and cleared by software. It controls the mapping of the TIM9_CH1 and
TIM9_CH2 alternate functions onto the GPIO ports.
0: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3)
1: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6)
Reserved.
24 23 22
Reserved
8 7 6
TIM13_ TIM11_ TIM10_
REMA REMA REMA
P P P
rw rw rw
DocID13902 Rev 15
21 20 19
5 4 3
TIM9_
REMA
Reserved
P
rw
RM0008
18 17 16
2 1 0