Figure 259. Lsb Justified 24-Bit Frame Length With Cpol = 0; Figure 260. Operations Required To Transmit 0X3478Ae; Figure 261. Operations Required To Receive 0X3478Ae - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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In transmission mode:

If data 0x3478AE have to be transmitted, two write operations to the SPI_DR register

are required from software or by DMA. The operations are shown below.

In reception mode:

If data 0x3478AE are received, two successive read operations from SPI_DR are

required on each RXNE event.

Figure 259. LSB Justified 24-bit frame length with CPOL = 0

Channel left 32-bit

First write to Data register

conditioned by TXE = '1'

Only the 8 LSB bits of the half-word

are significant. Whatever the 8 MSBs

a field of 0x00 is forced instead

First read from Data register

conditioned by RXNE = '1'

Only the 8 LSB bits of the half-word

are significant. Whatever the 8 MSBs,

a field of 0x00 is forced instead

DocID13902 Rev 15

Serial peripheral interface (SPI)

Transmission

24-bit remaining

Second write to Data register

conditioned by TXE = '1'

Second read from Data register

conditioned by RXNE = '1'

Channel right

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