Table 73. Dac Pins; Figure 40. Dac Channel Block Diagram - ST STM32F101 series Reference Manual

RM0008
EXTI_9
V
DDA
V
SSA
V
R EF+
1. In connectivity line devices, the TIM8_TRGO trigger is replaced by TIM3_TRGO .
Name
V
REF+
V
DDA
V
SSA
DAC_OUTx
Note: Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is
automatically connected to the analog converter output (DAC_OUTx). In order to avoid
parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).

Figure 40. DAC channel block diagram

TSELx[2:0] bits
SWTR IGx
TIM2_T RGO
TIM4_T RGO
TIM5_T RGO
TIM6_T RGO
TIM7_T RGO
(1)
TIM8_T RGO
12-bit
DHRx
Signal type
Input, analog reference
positive
Input, analog supply
Input, analog supply
ground
Analog output signal
DocID13902 Rev 15
Digital-to-analog converter (DAC)
DMAENx
DM A req ue stx
Control logicx
trianglex
LFSRx
12-bit
DORx
12-bit
Digital-to-analog
converterx

Table 73. DAC pins

The higher/positive reference voltage for the DAC,
≤ ≤
2.4 V V + V
REF DDA
Analog power supply
Ground for analog power supply
DAC channelx analog output
DAC control register
TENx
MAMPx[3:0] bits
WAVENx[1:0] bits
Remarks
(3.3 V)
DAC_ OU Tx
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