Clock Security System (Css); Rtc Clock; Watchdog Clock - ST STM32F101 series Reference Manual

Connectivity line devices: reset and clock control (RCC)
8.2.7

Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
a failure is detected on the HSE clock, the HSE Oscillator is automatically disabled, a clock
failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is
generated to inform the software about the failure (Clock Security System Interrupt CSSI),
allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex
(Non-Maskable Interrupt) exception vector.
Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is
automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock directly or through PLL2, and the PLL clock is used as system
clock), a detected failure causes a switch of the system clock to the HSI oscillator and the
disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the
clock entry of the PLL (directly or through PLL2) used as system clock when the failure
occurs, the PLL is disabled too.
8.2.8

RTC clock

The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected
by programming the RTCSEL[1:0] bits in the
This selection cannot be modified without resetting the Backup domain.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
•
If LSE is selected as RTC clock:
–
•
If LSI is selected as Auto-Wakeup unit (AWU) clock:
–
•
If the HSE clock divided by 128 is used as RTC clock:
–
–
8.2.9

Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
131/1128
Clock interrupt register
The RTC continues to work even if the V
V supply is maintained.
BAT
The AWU state is not guaranteed if the V
Section 8.2.5: LSI clock on page 130
The RTC state is not guaranteed if the V
voltage regulator is powered off (removing power from the 1.8 V domain).
The DPB bit (Disable backup domain write protection) in the Power controller
register must be set to 1 (refer to
(PWR_CR)).
DocID13902 Rev 15
(RCC_CIR).
Backup domain control register
supply is switched off, provided the
DD
supply is powered off. Refer to
DD
for more details on LSI calibration.
supply is powered off or if the internal
DD
Section 5.4.1: Power control register
RM0008
®
-M3 NMI
(RCC_BDCR).