Iwdg Register Map; Table 97. Iwdg Register Map And Reset Values - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus
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RM0008
19.4.5

IWDG register map

The following table gives the IWDG register map and reset values.
Offset
Register
IWDG_KR
0x00
Reset value
IWDG_PR
0x04
Reset value
IWDG_RLR
0x08
Reset value
IWDG_SR
0x0C
Reset value
Refer to

Table 97. IWDG register map and reset values

Reserved
Reserved
Table 3 on page 51
for the register boundary addresses.
0
Reserved
Reserved
DocID13902 Rev 15
Independent watchdog (IWDG)
KEY[15:0]
0
0
0
0
0
0
0
0
0
RL[11:0]
1
1
1
1
1
1
0
0
0
0
0
0
PR[2:0]
0
0
0
1
1
1
1
1
1
0
0
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