Table 113. Fsmc_Bwtrx Bit Fields; Figure 191. Mode2 And Mode B Read Accesses - ST STM32F101 series Reference Manual

Flexible static memory controller (FSMC)
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Mode 2/B - NOR Flash
513/1128

Table 113. FSMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses, DATAST+3 HCLK cycles for read accesses).
DATAST
This value cannot be 0 (minimum is 1).
ADDHLD Don't care
Duration of the first access phase (ADDSET+1 HCLK cycles) for
ADDSET
write accesses.

Figure 191. Mode2 and mode B read accesses

A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
(ADDSET +1)
HCLK cycles
DocID13902 Rev 15
Value to set
Memory transaction
data driven
by memory
(DATAST + 1)
HCLK cycles
Data sampled
RM0008
2 HCLK
cycles
Data strobe
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