Buffer Descriptor Table - ST STM32F101 series Reference Manual

RM0008
23.5.3

Buffer descriptor table

Although the buffer descriptor table is located inside the packet buffer memory, its entries
can be considered as additional registers used to configure the location and size of the
packet buffers used to exchange data between the USB macro cell and the STM32F10xxx.
Due to the common APB bridge limitation on word addressability, all packet memory
locations are accessed by the APB using 32-bit aligned addresses, instead of the actual
memory location addresses utilized by the USB peripheral for the USB_BTABLE register
and buffer description table locations.
In the following pages two location addresses are reported: the one to be used by
application software while accessing the packet memory, and the local one relative to USB
Peripheral access. To obtain the correct STM32F10xxx memory address value to be used in
the application software while accessing the packet memory, the actual memory location
address must be multiplied by two. The first packet memory location is located at
0x4000 6000. The buffer descriptor table entry associated with the USB_EPnR registers is
described below.
A thorough explanation of packet buffers and the buffer descriptor table usage can be found
in Structure and usage of packet buffers on page
Transmission buffer address n (USB_ADDRn_TX)
Address offset: [USB_BTABLE] + n*16
USB local address: [USB_BTABLE] + n*8
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Bits 15:1 ADDRn_TX[15:1]: Transmission buffer address
Bit 0 Must always be written as '0 since packet memory is word-wide and all packet buffers must be
word-aligned.
12 11 10 9
ADDRn_TX[15:1]
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These bits point to the starting address of the packet buffer containing data to be transmitted
by the endpoint associated with the USB_EPnR register at the next IN token addressed to it.
Universal serial bus full-speed device interface (USB)
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