ST STM32F101 series Reference Manual page 549

Flexible static memory controller (FSMC)
Bits 31:7
Bit 6 FEMPT: FIFO empty.
Bit 5 IFEN: Interrupt falling edge detection enable bit
Bit 4 ILEN: Interrupt high-level detection enable bit
Bit 3 IREN: Interrupt rising edge detection enable bit
Bit 2 IFS: Interrupt falling edge status
Bit 1 ILS: Interrupt high-level status
Bit 0 IRS: Interrupt rising edge status
Common memory space timing register 2..4 (FSMC_PMEM2..4)
Address offset: Address: 0xA000 0000 + 0x48 + 0x20 * (x – 1), x = 2..4
Reset value: 0xFCFC FCFC
Each FSMC_PMEMx (x = 2..4) read/write register contains the timing information for PC
Card or NAND Flash memory bank x, used for access to the common memory space of the
16-bit PC Card/CompactFlash, or to access the NAND Flash for command, address write
access and data read/write access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MEMHIZx
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
549/1128
Reserved, must be kept at reset value.
Read-only bit that provides the status of the FIFO
0: FIFO not empty
1: FIFO empty
0: Interrupt falling edge detection request disabled
1: Interrupt falling edge detection request enabled
0: Interrupt high-level detection request disabled
1: Interrupt high-level detection request enabled
0: Interrupt rising edge detection request disabled
1: Interrupt rising edge detection request enabled
The flag is set by hardware and reset by software.
0: No interrupt falling edge occurred
1: Interrupt falling edge occurred
The flag is set by hardware and reset by software.
0: No Interrupt high-level occurred
1: Interrupt high-level occurred
The flag is set by hardware and reset by software.
0: No interrupt rising edge occurred
1: Interrupt rising edge occurred
MEMHOLDx
DocID13902 Rev 15
9 8 7
MEMWAITx
RM0008
6 5 4 3 2 1 0
MEMSETx