Dma Register Map; Table 80. Dma Register Map And Reset Values - ST STM32F101 series Reference Manual

Direct memory access controller (DMA)
13.4.7

DMA register map

The following table gives the DMA register map and the reset values.
Offset Register
DMA_ISR
0x000
Reset value
DMA_IFCR
0x004
Reset value
DMA_CCR1
0x008
Reset value
DMA_CNDTR1
0x00C
Reset value
DMA_CPAR1
0x010
Reset value 0
DMA_CMAR1
0x014
Reset value 0
0x018
DMA_CCR2
0x01C
Reset value
DMA_CNDTR2
0x020
Reset value
DMA_CPAR2
0x024
Reset value 0
DMA_CMAR2
0x028
Reset value 0
0x02C
DMA_CCR3
0x030
Reset value
DMA_CNDTR3
0x034
Reset value
DMA_CPAR3
0x038
Reset value 0
289/1128

Table 80. DMA register map and reset values

Reserved
0 0 0 0 0
Reserved
0 0 0 0 0
Reserved
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reserved
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reserved
Reserved
0 0 0 0 0 0 0 0
DocID13902 Rev 15
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
Reserved
0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
Reserved
0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
RM0008
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0