Table 211. Tx Interface Signal Encoding; Table 212. Rx Interface Signal Encoding - ST STM32F101 series Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
deasserted and MII_RX_ER is asserted, a specific MII_RXD[3:0] value is used to
transfer specific information from the PHY (see
•
MII_RX_DV: receive data valid indicates that the PHY is presenting recovered and
decoded nibbles on the MII for reception. It must be asserted synchronously
(MII_RX_CLK) with the first recovered nibble of the frame and must remain asserted
through the final recovered nibble. It must be deasserted prior to the first clock cycle
that follows the final nibble. In order to receive the frame correctly, the MII_RX_DV
signal must encompass the frame, starting no later than the SFD field.
•
MII_RX_ER: receive error must be asserted for one or more clock periods
(MII_RX_CLK) to indicate to the MAC sublayer that an error was detected somewhere
in the frame. This error condition must be qualified by MII_RX_DV assertion as
described in
MII_TX_EN
0
1
MII_RX_DV
0
0
0
0
0
1
1
MII clock sources
To generate both TX_CLK and RX_CLK clock signals, the external PHY must be clocked
with an external 25 MHz as shown in
quartz to provide this clock, the STM32F10xxx microcontroller can output this signal on its
MCO pin. In this case, the PLL multiplier has to be configured so as to get the desired
frequency on the MCO pin, from the 25 MHz external quartz.
967/1128
Table 212.

Table 211. TX interface signal encoding

MII_TXD[3:0]
0000 through 1111
0000 through 1111

Table 212. RX interface signal encoding

MII_RX_ERR MII_RXD[3:0]
0 0000 through 1111
1
1 0001 through 1101
1
1
0 0000 through 1111
1 0000 through 1111
DocID13902 Rev 15
Table 212).
Normal inter-frame
Normal data transmission
Normal inter-frame
0000 Normal inter-frame
Reserved
1110 False carrier indication
1111 Reserved
Normal data reception
Data reception with errors
Figure 331. Instead of using an external 25 MHz
Description
Description
RM0008