Smbus; Table 188. Smbus Vs. I2C - ST STM32F101 series Reference Manual

Inter-integrated circuit (I
26.3.6

SMBus

Introduction
The System Management Bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on I
principles of operation. SMBus provides a control bus for system and power management
related tasks. A system may use SMBus to pass messages to and from devices instead of
toggling individual control lines.
The System Management Bus Specification refers to three types of devices. A slave is a
device that is receiving or responding to a command. A master is a device that issues
commands, generates the clocks, and terminates the transfer. A host is a specialized
master that provides the main interface to the system's CPU. A host must be a master-slave
and must support the SMBus host notify protocol. Only one host is allowed in a system.
Similarities between SMBus and I
•
2 wire bus protocol (1 Clk, 1 Data) + SMBus Alert line optional
• Master-slave communication, Master provides clock
•
Multi master capability
• SMBus data format similar to I
Differences between SMBus and I
The following table describes the differences between SMBus and I
Max. speed 100 kHz
Min. clock speed 10 kHz
35 ms clock low timeout
Logic levels are fixed
Different address types (reserved, dynamic etc.)
Different bus protocols (quick command, process
call etc.)
SMBus application usage
With System Management Bus, a device can provide manufacturer information, tell the
system what its model/part number is, save its state for a suspend event, report different
types of errors, accept control parameters, and return its status. SMBus provides a control
bus for system and power management related tasks.
Device identification
Any device that exists on the System Management Bus as a slave has a unique address
called the Slave Address. For the list of reserved slave addresses, refer to the SMBus
specification version. 2.0 (http://smbus.org/).
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2
C) interface
Table 188. SMBus vs. I
SMBus
DocID13902 Rev 15
2
C
2
C 7-bit addressing format
2
C
2
Max. speed 400 kHz
No minimum clock speed
No timeout
Logic levels are V
7-bit, 10-bit and general call slave address types
No bus protocols
(Figure 268).
2
C.
C
2
I C
dependent
DD
RM0008
2
C