I 2 C Debug Mode; I 2 C Registers; C Control Register 1 (I2C_Cr1) - ST STM32F101 series Reference Manual

Inter-integrated circuit (I
2
26.5 I C debug mode
When the microcontroller enters the debug mode (Cortex
timeout either continues to work normally or stops, depending on the
DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details,
refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C on
page 1091.
2
26.6 I C registers
Refer to
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
2
26.6.1 I

C Control register 1 (I2C_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13 12
SWRST ALERT PEC
Res.
rw rw rw
Bit 15 SWRST: Software reset
Note: This bit can be used to reinitialize the peripheral after an error or a locked state. As an
Bit 14 Reserved, must be kept at reset value
Bit 13 ALERT: SMBus alert
Bit 12 PEC: Packet error checking
Note: PEC calculation is corrupted by an arbitration loss.
765/1128
2
C) interface
Table 2.1 on page 47
11 10 9
POS ACK STOP START
rw rw rw
When set, the I2C is under reset state. Before resetting this bit, make sure the I2C lines are
released and the bus is free.
2
0: I C Peripheral not under reset
2
1: I C Peripheral under reset state
example, if the BUSY bit is set and remains locked due to a glitch on the bus, the
SWRST bit can be used to exit from this state.
This bit is set and cleared by software, and cleared by hardware when PE=0.
0: Releases SMBA pin high. Alert Response Address Header followed by NACK.
1: Drives SMBA pin low. Alert Response Address Header followed by ACK.
This bit is set and cleared by software, and cleared by hardware when PEC is transferred or
by a START or Stop condition or when PE=0.
0: No PEC transfer
1: PEC transfer (in Tx or Rx mode)
for a list of abbreviations used in register descriptions.
8 7 6
NO
ENGC ENPEC ENARP
STRETCH
rw rw rw
DocID13902 Rev 15
®
-M3 core halted), the SMBUS
5 4 3 2
SMB
TYPE
Res.
rw rw rw
RM0008
1 0
SMBU
PE
S
rw rw