Clock Interrupt Register (Rcc_Cir) - ST STM32F101 series Reference Manual

Connectivity line devices: reset and clock control (RCC)
Bits 7:4 HPRE[3:0]: AHB prescaler
Set and cleared by software to control AHB clock division factor.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock.
Refer to the section
Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
Bits 3:2 SWS[1:0]: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: Not applicable
Bits 1:0 SW[1:0]: System clock Switch
Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of
the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is
enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: Not allowed
8.3.3

Clock interrupt register (RCC_CIR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
15 14 13
PLL3 PLL2 PLL
RDYIE RDYIE RDYIE
Res.
rw rw
137/1128
Reading the Flash memory on page 59
28 27 26 25
Reserved
12 11 10 9
HSE HSI LSE
RDYIE RDYIE RDYIE
rw rw rw rw
DocID13902 Rev 15
24 23 22 21
PLL3 PLL2
CSSC
RDYC RDYC
w w w
8 7 6 5
LSI PLL3 PLL2
CSSF
RDYIE RDYF RDYF
rw r r
for more details.
20 19 18
PLL HSE HSI
RDYC RDYC RDYC
w w w
4 3 2
PLL HSE HSI
RDYF RDYF RDYF
r r r r
RM0008
17 16
LSE LSI
RDYC RDYC
w w
1 0
LSE LSI
RDYF RDYF
r r