Figure 235. Event Flags And Interrupt Generation - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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The transmit interrupt can be generated by the following events:

The FIFO 0 interrupt can be generated by the following events:

The FIFO 1 interrupt can be generated by the following events:

The error and status change interrupt can be generated by the following events:

Figure 235. Event flags and interrupt generation

Transmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set.

Transmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set.

Transmit mailbox 2 becomes empty, RQCP2 bit in the CAN_TSR register set.

Reception of a new message, FMP0 bits in the CAN_RF0R register are not '00'.

FIFO0 full condition, FULL0 bit in the CAN_RF0R register set.

FIFO0 overrun condition, FOVR0 bit in the CAN_RF0R register set.

Reception of a new message, FMP1 bits in the CAN_RF1R register are not '00'.

FIFO1 full condition, FULL1 bit in the CAN_RF1R register set.

FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.

Error condition, for more details on error conditions please refer to the CAN Error

Status register (CAN_ESR).

DocID13902 Rev 15

Controller area network (bxCAN)

STATUS CHANGE

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