Figure 103. Counter Timing Diagram, Internal Clock Divided By 1; Figure 104. Counter Timing Diagram, Internal Clock Divided By 2; Figure 105. Counter Timing Diagram, Internal Clock Divided By 4 - ST STM32F101 series Reference Manual

General-purpose timers (TIM2 to TIM5)
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Figure 103. Counter timing diagram, internal clock divided by 1

CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 104. Counter timing diagram, internal clock divided by 2

CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 105. Counter timing diagram, internal clock divided by 4

CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
DocID13902 Rev 15
31 32 33 34 35 36 00 01 02 03 04 05 06 07
0034 0035 0036 0000 0001 0002 0003
0035
0036
RM0008
0000 0001