Figure 120. Control Circuit In Normal Mode, Internal Clock Divided By 1; Figure 121. Ti2 External Clock Connection Example - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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General-purpose timers (TIM2 to TIM5)

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the

CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual

control bits and can be changed only by software (except UG which remains cleared

automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal

clock CK_INT.

without prescaler.

Figure 120. Control circuit in normal mode, internal clock divided by 1

Counter clock = CK_CNT = CK_PSC

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at

each rising or falling edge on a selected input.

For example, to configure the upcounter to count in response to a rising edge on the TI2

input, use the following procedure:

Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= '01 in the

TIMx_CCMR1 register.

Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1

shows the behavior of the control circuit and the upcounter in normal mode,

COUNTER REGISTER

TI2F_Falling

32 33 34 35 36

DocID13902 Rev 15

01 02 03 04 05 06 07

external clock

external clock

internal clock

(internal clock)

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