Clock Selection - ST STM32F101 series Reference Manual

General-purpose timers (TIM9 to TIM14)
Figure 155. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
16.3.3

Clock selection

The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1 (for TIM9 and TIM12): external input pin (TIx)
•
Internal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from
another timer. Refer to
details.
Internal clock source (CK_INT)
The internal clock source is the default clock source for TIM10/TIM11 and TIM13/TIM14.
For TIM9 and TIM12, the internal clock source is selected when the slave mode controller is
disabled (SMS='000'). The CEN bit in the TIMx_CR1 register and the UG bit in the
TIMx_EGR register are then used as control bits and can be changed only by software
(except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the
prescaler is clocked by the internal clock CK_INT.
Figure 156
without prescaler.
425/1128
CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
Write a new value in TIMx_ARR
Section : Using one timer as prescaler for another
shows the behavior of the control circuit and the upcounter in normal mode,
DocID13902 Rev 15
preloaded)
CEN
F0 F1 F2 F3 F4 F5
F5
F5
00 01 02 03 04 05 06 07
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for more
RM0008