Host-Mode Registers - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32F101 series:

Table of Contents

USB on-the-go full-speed (OTG_FS)

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx)

(x = 1..3, where x is the FIFO_number)

Address offset: 0x104 + (FIFO_number – 1) × 0x04

Reset value: 0x02000400

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bits 31:16 INEPTXFD: IN endpoint TxFIFO depth

Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address

Host-mode registers

Bit values in the register descriptions are expressed in binary unless otherwise specified.

Host-mode registers affect the operation of the core in the host mode. Host mode registers

must not be accessed in device mode, as the results are undefined. Host mode registers

can be categorized as follows:

OTG_FS Host configuration register (OTG_FS_HCFG)

Address offset: 0x400

Reset value: 0x0000 0000

This register configures the core after power-on. Do not make changes to this register after

initializing the host.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 FSLSS: FS- and LS-only support

This value is in terms of 32-bit words.

Minimum value is 16

The power-on reset value of this register is specified as the largest IN endpoint FIFO

number depth.

This field contains the memory start address for IN endpoint transmit FIFOx. The address

must be aligned with a 32-bit memory location.

The application uses this bit to control the core's enumeration speed. Using this bit, the

application can make the core enumerate as an FS host, even if the connected device

supports HS traffic. Do not make changes to this field after initial programming.

1: FS/LS-only, even if the connected device can support HS (read-only)

DocID13902 Rev 15