External Memory Interface Signals; Table 104. Programmable Nor/Psram Access Parameters; Table 105. Nonmultiplexed I/O Nor Flash - ST STM32F101 series Reference Manual

Flexible static memory controller (FSMC)
Parameter
Address
setup
Address hold
Data setup
Bust turn
Clock divide
ratio
Data latency
21.5.1

External memory interface signals

Table 105,
Flash, SRAM and PSRAM.
Note: Prefix "N". specifies the associated signal as active low.
NOR Flash, nonmultiplexed I/Os
CLK
A[25:0]
D[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT
NOR Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
505/1128

Table 104. Programmable NOR/PSRAM access parameters

Function
Duration of the address
setup phase
Duration of the address hold
phase
Duration of the data setup
phase
Duration of the bus
turnaround phase
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Number of clock cycles to
issue to the memory before
the first data of the burst
Table 106 and Table 107

Table 105. Nonmultiplexed I/O NOR Flash

FSMC signal name
DocID13902 Rev 15
Access mode
Asynchronous
Asynchronous,
muxed I/Os
Asynchronous
Asynchronous and
synchronous read
Synchronous
Synchronous
list the signals that are typically used to interface NOR
I/O
O Clock (for synchronous access)
O Address bus
I/O Bidirectional data bus
O Chip select, x = 1..4
O Output enable
O Write enable
Latch enable (this signal is called address
O
valid, NADV, by some NOR Flash devices)
I NOR Flash wait input signal to the FSMC
Unit Min.
AHB clock cycle
1
(HCLK)
AHB clock cycle
2
(HCLK)
AHB clock cycle
2
(HCLK)
AHB clock cycle
1
(HCLK)
AHB clock cycle
2
(HCLK)
Memory clock
2
cycle (CLK)
Function
RM0008
Max.
16
16
256
16
16
17