Interrupts and events
10.3.3
Rising trigger selection register (EXTI_RTSR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
15
14
13
TR15
TR14
TR13
TR12
rw
rw
rw
Bits 31:20
Bits 19:0 TRx: Rising trigger event configuration bit of line x
Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.
Note:
The external wakeup lines are edge triggered, no glitches must be generated on these lines.
If a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the
pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
10.3.4
Falling trigger selection register (EXTI_FTSR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
15
14
13
TR15
TR14
TR13
TR12
rw
rw
rw
Bits 31:20
Reserved, must be kept at reset value (0).
Bits 19:0 TRx: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Note: Bit 19 used in connectivity line devices and is reserved otherwise.
Note:
The external wakeup lines are edge triggered, no glitches must be generated on these lines.
If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the
pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
211/1128
28
27
26
25
Reserved
12
11
10
9
TR11
TR10
TR9
rw
rw
rw
rw
Reserved, must be kept at reset value (0).
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
28
27
26
25
Reserved
12
11
10
9
TR11
TR10
TR9
rw
rw
rw
rw
24
23
22
8
7
6
TR8
TR7
TR6
rw
rw
rw
24
23
22
8
7
6
TR8
TR7
TR6
rw
rw
rw
DocID13902 Rev 15
21
20
19
18
TR19
TR18
rw
rw
5
4
3
2
TR5
TR4
TR3
TR2
rw
rw
rw
rw
21
20
19
18
TR19
TR18
rw
rw
5
4
3
2
TR5
TR4
TR3
TR2
rw
rw
rw
rw
RM0008
17
16
TR17
TR16
rw
rw
1
0
TR1
TR0
rw
rw
17
16
TR17
TR16
rw
rw
1
0
TR1
TR0
rw
rw
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