Table 209. Management Frame Format; Figure 327. Smi Interface Signals - ST STM32F101 series Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
The application can select one of the 32 PHYs and one of the 32 registers within any PHY
and send control data or receive status information. Only one register in one PHY can be
addressed at any given time.
Both the MDC clock line and the MDIO data line are implemented as alternate function I/O
in the microcontroller:
•
MDC: a periodic clock that provides the timing reference for the data transfer at the
maximum frequency of 2.5 MHz. The minimum high and low times for MDC must be
160 ns each, and the minimum period for MDC must be 400 ns. In idle state the SMI
management interface drives the MDC clock signal low.
•
MDIO: data input/output bitstream to transfer status information to/from the PHY device
synchronously with the MDC clock signal
SMI frame format
The frame structure related to a read or write operation is shown in
transmission must be from left to right.
Read
Write
963/1128

Figure 327. SMI interface signals

Table 209. Management frame format

Preamble
Start Operation PADDR RADDR
(32 bits)
1... 1 01
1... 1 01
DocID13902 Rev 15
Management frame fields
10 ppppp rrrrr
01 ppppp rrrrr
RM0008
Table 13, the order of bit
TA Data (16 bits)
Z0 ddddddddddddddd
10 ddddddddddddddd
Idle
Z
Z