Rtc Alarm Register High (Rtc_Alrh / Rtc_Alrl) - ST STM32F101 series Reference Manual

Real-time clock (RTC)
18.4.6

RTC alarm register high (RTC_ALRH / RTC_ALRL)

When the programmable counter reaches the 32-bit value stored in the RTC_ALR register,
an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is
write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if
the RTOFF value is '1'.
RTC alarm register high (RTC_ALRH)
Address offset: 0x20
Write only (see
Reset value: 0xFFFF
15 14 13
w w w
Bits 15:0 RTC_ALR[31:16]: RTC alarm high
RTC alarm register low (RTC_ALRL)
Address offset: 0x24
Write only (see
Reset value: 0xFFFF
15 14 13
w w w
Bits 15:0 RTC_ALR[15:0]: RTC alarm low
The low part of the alarm time is written by software in this register. To write to this register it
is necessary to enter configuration mode (see
page
483/1128
Section 18.3.4 on page
12 11 10 9
w w w w
The high part of the alarm time is written by software in this register. To write to this register
it is necessary to enter configuration mode (see
on page 476).
Section 18.3.4 on page
12 11 10 9
w w w w
476).
476)
8 7 6
RTC_ALR[31:16]
w w w
476)
8 7 6
RTC_ALR[15:0]
w w w
Section 18.3.4: Configuring RTC registers on
DocID13902 Rev 15
5 4 3
w w w
Section 18.3.4: Configuring RTC registers
5 4 3
w w w
RM0008
2 1 0
w w w
2 1 0
w w w