Figure 315. Bulk/Control In Transactions - ST STM32F101 series Reference Manual

USB on-the-go full-speed (OTG_FS)
init _reg(ch_2)
set _ch_en
set _ch_en
set _ch_en
read_rx_sts
read_rx_fifo
set _ch_en
read_rx_stsre
read_rx_sts
read_rx_sts
De-allocate
The sequence of operations is as follows:
a)
b)
c)
d)
e)
921/1128

Figure 315. Bulk/control IN transactions

Application
1
init_reg(ch _1)
1
write_tx_fifo
(ch_1)
2
(ch _2)
2
write_tx_fifo
(ch_1)
5
(ch _2)
(ch _2)
5
(ch _2)
7
De-allocate
(ch_1)
ad_rx_fifo
7
Disable
(ch _2) 9
11
(ch _2) 13
Initialize channel 2.
Set the CHENA bit in HCCHAR2 to write an IN request to the non-periodic request
queue.
The core attempts to send an IN token after completing the current OUT
transaction.
The core generates an RXFLVL interrupt as soon as the received packet is written
to the receive FIFO.
In response to the RXFLVL interrupt, mask the RXFLVL interrupt and read the
received packet status to determine the number of bytes received, then read the
receive FIFO accordingly. Following this, unmask the RXFLVL interrupt.
AHB
1
MPS
1
MPS
RXFLVL interrupt
1
MPS
RXFLVL interrupt
6
1
MPS
8
RXFLVL interrupt
RXFLVL interrupt
10
CHH interrupt r
12
DocID13902 Rev 15
Host USB
Non-Periodic Request
Queue
4
Assume that this queue
3
can hold 4 entries.
ch_1
ch_2
ch_1
ch_2
3
4
ch_1
ch_2
ch_2
ch_2
6
ch_2
RM0008
Device
ai15675