ST STM32F101 series Reference Manual page 138

RM0008
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
Bit 22 PLL3RDYC: PLL3 Ready Interrupt Clear
Bit 21 PLL2RDYC: PLL2 Ready Interrupt Clear
Bit 20 PLLRDYC: PLL ready interrupt clear
Bit 19 HSERDYC: HSE ready interrupt clear
Bit 18 HSIRDYC: HSI ready interrupt clear
Bit 17 LSERDYC: LSE ready interrupt clear
Bit 16 LSIRDYC: LSI ready interrupt clear
Bit 15 Reserved, must be kept at reset value.
Bit 14 PLL3RDYIE: PLL3 Ready Interrupt Enable
Bit 13 PLL2RDYIE: PLL2 Ready Interrupt Enable
Bit 12 PLLRDYIE: PLL ready interrupt enable
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
This bit is set by software to clear the PLL3RDYF flag.
0: No effect
1: Clear PLL3RDYF flag
This bit is set by software to clear the PLL2RDYF flag.
0: No effect
1: Clear PLL2RDYF flag
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
This bit is set by software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: Clear LSERDYF flag
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: Clear LSIRDYF flag
Set and cleared by software to enable/disable interrupt caused by PLL3 lock.
0: PLL3 lock interrupt disabled
1: PLL3 lock interrupt enabled
Set and cleared by software to enable/disable interrupt caused by PLL2 lock.
0: PLL2 lock interrupt disabled
1: PLL2 lock interrupt enabled
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Connectivity line devices: reset and clock control (RCC)
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