Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - ST STM32F101 series Reference Manual

RM0008
Bit 2 HSIRDYF: HSI ready interrupt flag
Bit 1 LSERDYF: LSE ready interrupt flag
Bit 0 LSIRDYF: LSI ready interrupt flag
7.3.4

APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29
15 14 13
ADC3 USART1 TIM8
RST RST RST
rw rw rw
Bits 31:22
Bit 21 TIM11RST: TIM11 timer reset
Bit 20 TIM10RST: TIM10 timer reset
Bit 19 TIM9RST: TIM9 timer reset
Bits 18:16
Low-, medium-, high- and XL-density reset and clock control (RCC)
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is
set.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the internal 8 MHz RC oscillator
1: Clock ready interrupt caused by the internal 8 MHz RC oscillator
Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is
set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the external 32 kHz oscillator
1: Clock ready interrupt caused by the external 32 kHz oscillator
Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the internal RC 40 kHz oscillator
1: Clock ready interrupt caused by the internal RC 40 kHz oscillator
28 27 26 25
Reserved
12 11 10 9
SPI1 TIM1 ADC2 ADC1
RST RST RST RST
rw rw rw rw
Reserved, must be kept at reset value.
Set and cleared by software.
0: No effect
1: Reset TIM11 timer
Set and cleared by software.
0: No effect
1: Reset TIM10 timer
Set and cleared by software.
0: No effect
1: Reset TIM9 timer
Reserved, always read as 0.
24 23 22
8 7 6
IOPG IOPF IOPE
RST RST RST
rw
rw rw
DocID13902 Rev 15
21 20 19 18
TIM11 TIM10 TIM9
RST RST RST
rw rw rw
5 4 3 2
IOPD IOPC IOPB IOPA
RST RST RST RST
rw rw rw rw
17 16
Reserved
1 0
AFIO
Res.
RST
Res.
rw
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