ST STM32F101 series Reference Manual page 144

RM0008
Bit 11 WWDGRST: Window watchdog reset
Bits 10:6 Reserved, must be kept at reset value.
Bit 5 TIM7RST: Timer 7 reset
Bit 4 TIM6RST: Timer 6 reset
Bit 3 TIM5RST: Timer 5 reset
Bit 2 TIM4RST: Timer 4 reset
Bit 1 TIM3RST: Timer 3 reset
Bit 0 TIM2RST: Timer 2 reset
Set and cleared by software.
0: No effect
1: Reset window watchdog
Set and cleared by software.
0: No effect
1: Reset timer 7
Set and cleared by software.
0: No effect
1: Reset timer 6
Set and cleared by software.
0: No effect
1: Reset timer 5
Set and cleared by software.
0: No effect
1: Reset timer 4
Set and cleared by software.
0: No effect
1: Reset timer 3
Set and cleared by software.
0: No effect
1: Reset timer 2
DocID13902 Rev 15
Connectivity line devices: reset and clock control (RCC)
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