Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - ST STM32F101 series Reference Manual

Connectivity line devices: reset and clock control (RCC)
8.3.4

APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29
15 14 13
USART1
RST
Res. Res.
rw
Bits 31:15
Bit 14 USART1RST: USART1 reset
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI 1 reset
Bit 11 TIM1RST: TIM1 timer reset
Bit 10 ADC2RST: ADC 2 interface reset
Bit 9 ADC1RST: ADC 1 interface reset
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 IOPERST: I/O port E reset
Bit 5 IOPDRST: I/O port D reset
141/1128
28 27 26 25
12 11 10 9
SPI1 TIM1 ADC2 ADC1
RST RST RST RST
rw rw rw rw
Reserved, must be kept at reset value.
Set and cleared by software.
0: No effect
1: Reset USART1
Set and cleared by software.
0: No effect
1: Reset SPI 1
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Set and cleared by software.
0: No effect
1: Reset ADC 2 interface
Set and cleared by software.
0: No effect
1: Reset ADC 1 interface
Set and cleared by software.
0: No effect
1: Reset I:O port E
Set and cleared by software.
0: No effect
1: Reset I/O port D
24 23 22
Reserved
8 7 6
IOPE
RST
Reserved
rw
DocID13902 Rev 15
21 20 19 18
5 4 3 2
IOPD IOPC IOPB IOPA
RST RST RST RST
rw rw rw rw
RM0008
17 16
1 0
AFIO
RST
Res.
rw