Figure 275. Method 2: Transfer Sequence Diagram For Master Receiver When N=2 - ST STM32F101 series Reference Manual

RM0008
The procedure described above is valid for N>2. The cases where a single byte or two bytes
are to be received should be handled differently, as described below:
•
Case of a single byte to be received:
–
–
–
–
•
Case of two bytes to be received:
–
–
–
–
–
–
–

Figure 275. Method 2: transfer sequence diagram for master receiver when N=2

7- bit master receiver
10- bit master receiver
S
Legend: S = Start, S
EVx = Event (with interrupt if ITEVFEN = 1)
EV5: SB=1, cleared by reading SR1 register followed by writing the DR register.
EV6: ADDR1, cleared by reading SR1 register followed by reading SR2.
In 10-bit master receiver mode, this sequence should be followed by writing CR2 with START = 1.
EV6_1: No associated flag event. The acknowledge disable should be done just after EV6, that is after ADDR is cleared.
EV7_3: BTF = 1, program STOP = 1, read DR twice (Read Data1 and Data2) just after programming the STOP.
EV9: ADD10= 1, cleared by reading SR1 register followed by writing DR register.
1. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.
2. The EV6_1 software sequence must complete before the ACK pulse of the current byte transfer.
In the ADDR event, clear the ACK bit.
Clear ADDR
Program the STOP/START bit.
Read the data after the RxNE flag is set.
Set POS and ACK
Wait for the ADDR flag to be set
Clear ADDR
Clear ACK
Wait for BTF to be set
Program STOP
Read DR twice
S Address A Data1
EV5 EV6 EV6_1
Header A Address
EV5 EV9
S
r
EV5
= Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge,
r
DocID13902 Rev 15
Inter-integrated circuit (I
A Data2 NA P
EV7_3
A
EV6
Header A
Data1 A
EV6
EV6_1
Data2 NA P
EV7_3
2
C) interface
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