ST STM32F101 series Reference Manual page 773

Inter-integrated circuit (I
Bit 3 ADD10: 10-bit header sent (Master mode)
– Set by hardware when the master has sent the first byte in 10-bit address mode.
– Cleared by software reading the SR1 register followed by a write in the DR register of the
Note: ADD10 bit is not set after a NACK reception
Bit 2 BTF: Byte transfer finished
– Set by hardware when NOSTRETCH=0 and:
– In reception when a new byte is received (including ACK pulse) and DR has not been read
– In transmission when a new byte should be sent and DR has not been written yet (TxE=1).
– Cleared by software reading SR1 followed by either a read or write in the DR register or by
Note: The BTF bit is not set after a NACK reception
Bit 1 ADDR: Address sent (master mode)/matched (slave mode)
– Set by hardware as soon as the received slave address matched with the OAR registers
Note: In slave mode, it is recommended to perform the complete clearing sequence (READ
– For 10-bit addressing, the bit is set after the ACK of the 2nd byte.
– For 7-bit addressing, the bit is set after the ACK of the byte.
Note: ADDR is not set after a NACK reception
Bit 0 SB: Start bit (Master mode)
– Set when a Start condition generated.
– Cleared by software by reading the SR1 register followed by writing the DR register, or by
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C) interface
0: No ADD10 event occurred.
1: Master has sent first address byte (header).
second address byte, or by hardware when PE=0.
0: Data byte transfer not done
1: Data byte transfer succeeded
yet (RxNE=1).
hardware after a start or a stop condition in transmission or when PE=0.
The BTF bit is not set if next byte to be transmitted is the PEC (TRA=1 in I2C_SR2
register and PEC=1 in I2C_CR1 register)
This bit is cleared by software reading SR1 register followed reading SR2, or by hardware
when PE=0.
Address matched (Slave)
0: Address mismatched or not received.
1: Received address matched.
content or a general call or a SMBus Device Default Address or SMBus Host or SMBus Alert
is recognized. (when enabled depending on configuration).
SR1 then READ SR2) after ADDR is set. Refer to
diagram for slave receiver on page
Address sent (Master)
0: No end of address transmission
1: End of address transmission
0: No Start condition
1: Start condition generated.
hardware when PE=0
DocID13902 Rev 15
Figure 271: Transfer sequence
749.
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