R1 (Normal Response Command); R1B; R2 (Cid, Csd Register); R3 (Ocr Register) - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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R1 (normal response command)

Code length = 48 bits. The 45:40 bits indicate the index of the command to be responded to,

this value being interpreted as a binary-coded number (between 0 and 63). The status of the

card is coded in 32 bits.

Bit position

It is identical to R1 with an optional busy signal transmitted on the data line. The card may

become busy after receiving these commands based on its state prior to the command

Code length = 136 bits. The contents of the CID register are sent as a response to the

CMD2 and CMD10 commands. The contents of the CSD register are sent as a response to

CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of

these registers is replaced by the end bit of the response. The card indicates that an erase

is in progress by holding MCDAT low. The actual erase time may be quite long, and the host

may issue CMD7 to deselect the card.

Bit position

Code length: 48 bits. The contents of the OCR register are sent as a response to CMD1.

The level coding is as follows: restricted voltage windows = low, card busy = low.

Secure digital input/output interface (SDIO)

DocID13902 Rev 15

Transmission bit

Command index

Transmission bit

Command index